Search - CRC verilog

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:

[VHDL-FPGA-Verilog] source_verilog

Description: verilog source crc criteria, such as CYXLIC REDUNDANCY -verilog source crc criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 265216 | Author: plo | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[VHDL-FPGA-Verilog] crc

Description: CRC-16 VHDL Source Code
Platform: | Size: 164864 | Author: kobin | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
Platform: | Size: 10240 | Author: | Hits:

[matlab] RFC_1622_CRC16_m

Description: RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with script to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
Platform: | Size: 1024 | Author: spaander | Hits:

[VHDL-FPGA-Verilog] crc

Description: 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Platform: | Size: 436224 | Author: 虎 | Hits:

[VHDL-FPGA-Verilog] CRC_outputlogic

Description: custom crc generater(verilog/vhdl)
Platform: | Size: 61440 | Author: li.yx | Hits:

[VHDL-FPGA-Verilog] CRCecoder

Description: CRC 编码的Verilog语言，高手的作品，放心下-CRC-coded Verilog language, master' s works, rest assured that the next
Platform: | Size: 1024 | Author: 王刚 | Hits:

[Program doc] crc_explain

Description: 循环冗余校验 CRC 的算法分析和程序实现。通信的目的是要把信息及时可靠地传送给对方，因此要求一个通信系统传输消息必须可靠与快速，在数字通信系统中可靠与快速往往是一对矛盾。为了解决可靠性，通信系统都采用了差错控制。本文详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实现-Cyclic Redundancy Check
Platform: | Size: 106496 | Author: 朱红 | Hits:

[Communication-Mobile] crc32_4

Description: 实现了crc功能的verilog源程序。可以综合。-verilog code for crc
Platform: | Size: 1024 | Author: tree | Hits:

[Mathimatics-Numerical algorithms] crc7

Description: CRC计算模块，7位CRC计算。经过FPGA及IC平台验证。-CRC calculation module, 7 CRC calculation. Through the FPGA and IC platform for verification.
Platform: | Size: 1024 | Author: liu | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 循环冗余码实现，用Verilog语言实现的，希望和大家分享-CRC implementation, using Verilog language, and would like to share
Platform: | Size: 76800 | Author: 叶亮 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码包括所有代码-Verilog code for CRC check reference design includes all the code
Platform: | Size: 10240 | Author: xuzunlei | Hits:

[VHDL-FPGA-Verilog] crc-gen[1]

Description: hamminag code using verilog this code is desinged for detecting
Platform: | Size: 60416 | Author: kim | Hits:

[VHDL-FPGA-Verilog] 54088960verilog_multicrc

Description: CRC校验码生成器的程序编码，verilog编写-The CRC generator to the program code, verilog write
Platform: | Size: 10240 | Author: 郝李鹏 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[Other systems] CRC-Verilog

Description: crc的verilog程序,希望可以帮到大家-crc of verilog
Platform: | Size: 4096 | Author: dongping | Hits:

[Other] crc-gen

Description: CRC的verilog电路生成软件，可以直接生成crc的verilog代码-CRC s verilog circuit generation software, you can generate the crc verilog code directly
Platform: | Size: 98304 | Author: jack ga | Hits:

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[VHDL-FPGA-Verilog] crc_verilog_xilinx

[Communication] crc_check

[VHDL-FPGA-Verilog] source_verilog

[Crack Hack] crc16

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[matlab] RFC_1622_CRC16_m

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] CRC_outputlogic

[VHDL-FPGA-Verilog] CRCecoder

[Program doc] crc_explain

[Communication-Mobile] crc32_4

[Mathimatics-Numerical algorithms] crc7

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] crc-gen[1]

[VHDL-FPGA-Verilog] 54088960verilog_multicrc

[VHDL-FPGA-Verilog] Perl_for_CRC

[Other systems] CRC-Verilog

[Other] crc-gen

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